Memory read methods, apparatus, and systems

ABSTRACT

Some embodiments include first memory cells and a first line used to access the first memory cells, second memory cells and at least one second line used to access the second memory cells. The first and second memory cells have a number of threshold voltage values corresponding to a number of states. The states represent values of information stored in the memory cells. During a read operation to read the first memory cells, a first voltage may be applied to the first line and a second voltage may be applied to the second line. At least one of the first and second voltages may include a value based on a change of at least one of the threshold voltage values changing from a first value to a second value. The first and second values may correspond to a unique state selected from all of the states. Other embodiments including additional apparatus, systems, and methods are disclosed.

BACKGROUND

Semiconductor devices such as flash memory devices are often present in computers and other electronic products (e.g., digital television, digital cameras, digital audio players, and memory cellular phones) to store data and other information. Flash memory devices may also be used as portable storage devices, such as portable Universal Serial Bus (USB) flash drives or “thumb” drives. Flash memory devices may retain the information stored in the device even when power is disconnected from the device.

A flash memory device stores information in numerous memory cells, which are usually formed in a semiconductor chip. Each of the memory cells often has a metal-oxide semiconductor (MOS) transistor with two different transistor gates: a control gate and a so-called “floating” gate. The control gate may be used to turn the transistor on and off to control access to the memory cell. The floating gate may be used to store one or more bits in each memory cell.

The number of electrons in the floating gate may determine the value of the information stored in memory cell. Different numbers of electrons in the floating gate may correspond to different values of information. The number of electrons in the floating gate may be varied by either adding electrons to or extracting electrons from the floating gate. A flash memory device usually has a programming operation (which is also sometimes referred to as a write operation) to add electrons to the floating gate, and an erase operation to extract electrons from the floating gate. Information in the memory cells may be read in a read operation. Each memory cell has a threshold voltage value dependent on the number of electrons in the floating gate. A read operation determines the threshold voltage value of the memory cell being read to provide the value of the information stored in the memory cell.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a memory device according to an embodiment of the invention.

FIG. 2 shows a partial schematic diagram of a memory device according to an embodiment of the invention.

FIG. 3 shows an example of threshold voltage value distribution of the memory device of FIG. 2.

FIG. 4 shows examples of changes in threshold voltage values of the memory device of FIG. 2.

FIG. 5 is a flow diagram showing methods of selecting values for a voltage to be applied to lines associated with selected memory cells of a memory device during a read operation according to an embodiment of the invention.

FIG. 6 is a flow diagram showing methods of selecting value for another voltage to be applied to lines associated with unselected memory cells of a memory device during a read operation according to an embodiment of the invention.

FIG. 7 shows a system according to an embodiment of the invention.

DETAILED DESCRIPTION

The inventor has discovered that in some cases, the threshold voltage values of the memory cells may change due to factors such as leakage in the memory cells, disturbances in the memory cells caused by programming and read operations, and the length of time that information has been stored in the memory cells. The change in the threshold voltage values may reduce the reliability of information read from the memory cells. The inventor has also discovered a variety of apparatus, systems, and methods that may be used to address at least a portion of these challenges, as explained in detail below.

FIG. 1 shows a block diagram of a memory device 100 according to an embodiment of the invention. Memory device 100 may include a memory array 102 with memory cells 103 arranged in rows and columns along with lines 104 and lines 105. Lines 104 and 105 may correspond to wordlines and bit lines, respectively, of a memory device. Memory device 100 may use lines 104 to access memory cells 103 and lines 105 to transfer information with memory cells 103. Row access and column access circuitry 107 and 108 may respond to an address register 112 to access memory cells 103 based on row address and column address signals on terminals 110, 111 or both. A data input/output circuit 114 may transfer data between memory cells 103 and terminals 110. Terminals 110 and 111 may be external terminals of memory device 100 (e.g., terminals exposed outside a chip or semiconductor package that contains memory device 100).

A control circuit 116 may control operations of memory device 100 based on signals present on terminals 110 and 111. A device (e.g., a processor or a memory controller) external to memory device 100 may send different commands (e.g., programming commands and read commands) to memory device 100 using different combinations of signals on terminals 110, 111, or both.

Memory device 100 may respond to the commands to perform operations such as programming, read, and erase operations. A programming operation may write data from terminals 110 to memory cells 103 (e.g., transfer data from terminals 110 to memory cells 103). A read operation may read data from memory cells 103 to terminals 110 (e.g., transfer data from memory cells 103 to terminals 110). An erase operation may erase data (e.g., clear data) from all memory cells 103 or from a portion of memory cells 103.

Memory device 100 may receive supply voltages Vcc and Vss. Vcc may include a positive voltage value, and Vss may include a ground potential. Memory device 100 may also include a voltage generator 140. Voltage generator 140 and control circuit 116 may act separately or together to provide different voltages to memory array 102 or to cause memory array 102 to receive different voltages during the operations (e.g., read operations) of memory device 100.

Memory device 100 may include an error correction unit 118 to check for errors in information read from memory cells 103. Error correction unit 118 may include error correction circuitry to correct errors based on error correction code (ECC), as is well-known to those of ordinary skill in the art. Memory device 100 may include a time keeper 119 to keep track of real time. The real time may be provided by a real-time clock, which may reside inside or outside memory device 100.

Memory device 100 may include a storage unit 120, which may include storage components such as flash memory cell components, read only memory (ROM) components, registers, and combinations thereof. Storage unit 120 may store data as a result of receiving different voltage values for use in operations such as read operations of memory device 100. Storage unit 120 may include a hardware portion, a firmware portion, or both, of memory device 100. Storage unit 120 may also be used to store codes (e.g., software programming instructions).

Memory device 100 may include a flash memory device such as a NAND flash or a NOR flash memory device, and other kinds of memory devices.

Memory device 100 may include a single-level-cell memory device such that memory cells 103 store information to represent a value of a single bit of data. For example, memory cells 103 may store information that represents either a binary “0” value or a binary “1” value of a single bit of data.

Memory device 100 may include a multi-level-cell (MLC) memory device such that memory cells 103 may store information to represent a value of multiple bits of data (e.g., a value of two, three, four, or some other number of bits of data). For example, when each of memory cells 103 is a two-bit per cell, each of memory cells 103 may store information to represent a value corresponding to one of four possible combinations of two bits of data (i.e., combination 00, 01, 10, and 11 of two bits of data). In another example, when each of memory cells 103 is a three-bit per cell, each of memory cells 103 may store information to represent a value corresponding to one of eight possible combinations of three bits of data (i.e., one of 000, 001, 010, 011, 100, 101, 110, and 111). In another example, when each of memory cells 103 is a four-bit per cell, each of memory cells 103 may store information to represent one of 16 possible binary combinations of four bits of data (i.e., one of 0000, 0001, 0010, 0011, 1000, and so on, up to 1111).

Single level and MLC memory devices may be combined within the device 100. One of ordinary skill in the art will readily recognize that memory device 100 may include other parts, which are omitted from FIG. 1 to help focus on the various embodiments described herein. Memory device 100 may include one or more of the embodiments described below with reference to FIG. 2 through FIG. 7.

As mentioned above, factors such as leakage in the memory cells, disturbances in the memory cells, and length of storage time, may cause the threshold voltage values of the memory cells to change. The change may reduce the reliability of information read from the memory cells. To help maintain the reliability of information read from memory cells 103 during a read operation, memory device 100 may read memory cells 103 using voltage values that are based on changes in the threshold voltage values of memory cells 103. Memory device 100 may include read operations that are similar to or identical to those described below with reference to FIG. 2 through FIG. 7.

FIG. 2 shows a partial schematic diagram of a memory device 200 according to an embodiment of the invention. Memory device 200 may be associated with memory device 100 of FIG. 1, perhaps forming a portion of memory array 102 of memory device 100. In FIG. 2, memory device 200 may include memory cells 210, 211, 212, and 213, arranged in rows 240, 241, 242, and 243, and columns 244, 245, and 246. The memory cells in the same column may be connected in a series (sometimes called a string) of memory cells, such as strings 250, 251, and 252. FIG. 2 shows an example of three strings with four memory cells in each string. The number of strings, memory cells, or both may vary.

As shown in FIG. 2, each of the memory cells may include a floating gate 208 and a control gate 209. Control gates 209 of memory cells in the same row (e.g., row 220) may be coupled to one of lines 260, 261, 262, and 263. These lines may correspond to portions of wordlines of a memory device. Memory device 200 may use lines 260, 261, 262, and 263 to access memory cells 210, 211, 212, and 213 during a read operation to read information stored in memory cells 210, 211, 212, and 213, and during a programming operation to write information into memory cells 210, 211, 212, and 213. Memory device 200 may use lines 270, 271, and 272 to transfer information to be stored into memory cells 210, 211, 212, and 213 during a programming operation, and to transfer the information read from these memory cells during a read operation. Memory device 200 may include transistors 281 and 282 (responsive to signals SELa and SELb, respectively) to couple strings 250, 251, and 252 to lines 270, 271, and 272 and line 291. Lines 270, 271, and 272 may correspond to portions of bit lines of a memory device. Line 291 may correspond to a portion of a source (voltage) line of a memory device. Line 291 may be coupled to a ground potential during a read operation.

Memory device 200 may write information into memory cells 210, 211, 212, and 213 in a programming operation. As mentioned above, the information stored in a memory cell (e.g., one of memory cells 210, 211, 212, and 213) depends on the number of electrons in the floating gate of the memory cell (e.g., floating gate 208).

Memory device 200 may read memory cells 210, 211, 212, and 213 during a read operation to obtain the information stored in these memory cells. Memory device 200 may determine the value of information read from these cells based on the number of electrons stored in these memory cells. During a read operation, memory device 200 may apply different voltages (e.g., voltages V1 and V2 in FIG. 2) to lines 260, 261, 262, and 263 to read selected memory cells among memory cells 210, 211, 212, and 213. In the description herein, selected memory cells refer to the memory cells that are selected to be read in a particular read operation, and unselected memory cells refer to the memory cells that are not selected to be read in that particular read operation. The values of the signals on terminals, such as terminals 110 and 111 of FIG. 1, may determine which memory cells are selected to be read in a read operation.

FIG. 2 shows an example where memory cells 211 are selected memory cells (to be read in a read operation) and the other memory cells 210, 212, and 213 are unselected memory cells (not to be read in the read operation). As shown in the example of FIG. 2, during a read operation, memory device 200 may apply voltage V1 to line 261 associated with the selected memory cells 211 and apply the same voltage V2 to other lines 260, 262, and 263 associated with the unselected memory cells 210, 212, and 213. In another example, if memory device 200 selects memory cells 213 (instead of memory cells 211) to be read during a read operation, then memory device 200 may apply voltage V1 to lines 263 associated with memory cells 213 and apply the same voltage V2 to other lines 260, 261, and 262 associated with the unselected memory cells 210, 211, and 213.

In the example shown in FIG. 2, memory device 200 may use a substantially constant value for voltage V2 (e.g. about five to six volts) to cause memory cells 210, 212, and 213 (unselected memory cells) to operate as pass elements during a read operation to pass information from memory cells 211 (selected memory cells) to lines 270, 271, and 272. As mentioned above, the value of the information stored in a memory cell may depend on the threshold voltage value of the memory cell. Memory device 200 may apply various values for V1 to read the selected memory cells based on the threshold voltage values of the selected memory cells (memory cells 211 in this example).

FIG. 3 shows an example of threshold voltage value distribution of memory device 200 of FIG. 2. Referring now to FIG. 2 and FIG. 3, it can be seen that Vt0 through Vt15 represent 16 different threshold voltage values that each of memory cells 210, 211, 212, and 213 may have when each of memory cells 210, 211, 212, and 213 is a 4-bit cell. Each of 16 threshold voltage values Vt0 through Vt15 in FIG. 3 may be within a different range of values. For example, threshold voltage value Vt1 may be within a range of values VL1 to VH1, threshold voltage value Vt2 may be within a range of values VL2 to VH2, and threshold voltage value Vt15 may be within a range of values VL15 to VH15.

Each of threshold voltage values Vt0 through Vt15 may correspond to one of 16 states (a state is sometimes called a level). In multiple bits, each state may represent one of a number of possible combinations of the multiple bits. For example, for four bits, each state may represent one of 16 combinations of the four bits. In FIG. 3, each of threshold voltage values Vt0 through Vt15 may correspond to one of 16 states, where each of 16 states may represent one of 16 combinations of four bits. For example, as shown in FIG. 3, state 0 may represent combination 1111, state 1 may represent combination 0111, and state 2 may represent combination 0010, state 14 may present combination 0110, and state 15 may present combination 1110. FIG. 3 shows each state representing a specific combination (e.g., state 1 representing combination 1110) as an example. Each state, however, may represent a combination that is different from the one shown in FIG. 3.

FIG. 3 also shows voltage values V1 ₀, V1 ₁, and V1 ₂ through V1 ₁₅, which may correspond to various values of V1 in FIG. 2 that memory device 200 may apply to line 261 during a read operation. Memory device 200 may use each of values V1 ₀, V1 ₁, and V1 ₂ through V1 ₁₅ to read information corresponding to one of threshold voltage values Vt0 through Vt15. For example, memory device 200 may use value V1 ₀, V1 ₁, and V1 ₁₅ to read information corresponding to threshold voltage values Vt0, Vt1, and Vt15, respectively. FIG. 3 shows value V1 ₁ being higher than zero volts as an example. Value V1 ₁, however, may include zero volts.

In FIG. 3, values V1 ₀, V1 ₁, and V1 ₂ through V1 ₁₅ are known values, which are based on the design and structure of the memory cells of the memory device 200. These values may be scaled linearly along the vertical axis (threshold voltage axis) of FIG. 3. For example, values V1 ₀, V1 ₁, and V1 ₂ through V1 ₁₅ may be scaled linearly such that V1 ₁ may have a value of 0.3 volt, V1 ₂ may have a value of 0.6 volt, V1 ₃ (not shown in FIG. 3) may have a value of 0.9 volt, V1 ₄ (not shown in FIG. 3) may have a value of 1.2 volts, V1 ₁₄ may have a value of 4.2 volts, and V1 ₁₅ may have a value of 4.5 volts. Values V1 ₀, V1 ₁, and V1 ₂ through V1 ₁₅ may be scaled in a nonlinear fashion.

During a read operation, memory device 200 (FIG. 2) may apply values V1 ₀, V1 ₁, and V1 ₂ through V1 ₁₅ of FIG. 3 to line 261 in a sequential fashion (e.g., from V1 ₀ to V1 ₁₅) to read information from the selected memory cells. Memory device 200 may read information from memory cells 210, 211, 212, and 213 using conventional techniques. However, memory device 200 may use voltage V1 or V2 (or both) during a read operation in which the value of voltage V1 or the value of voltage V2 (or both) may be selected by methods described below with reference to FIG. 4, FIG. 5, and FIG. 6.

As mentioned above, many factors may cause the threshold voltage values of the memory cells to change, thereby reducing the reliability of information read from the memory cells. In FIG. 3, threshold voltage values Vt0 through Vt15 memory cells 210, 211, 212, and 213 may change. To help maintain the reliability of information read from memory cells 210, 211, 212, and 213 when threshold voltage values Vt0 through Vt15 change, memory device 200 may read memory cells 210, 211, 212, and 213 using a value of voltage V2 and various values of voltage V1 in which the values of voltages V1 and V2 may be based on changes in the threshold voltage values Vt0 through Vt15.

Memory device 200 may have selectable values for voltage V1, selected in ways described below with reference to FIG. 4 and FIG. 5. Memory device 200 may operate to select the value for voltage V2 in ways described below with reference to FIG. 6.

FIG. 4 shows examples of changes in threshold voltage values of memory device 200 of FIG. 2. Thus, the threshold voltage values Vt0 through Vt15 (also shown in FIG. 3) may change to Vt′0 through Vt′15. The arrows in FIG. 4 symbolically indicate the changes in the threshold voltage values.

Value Vt_(NEUTRAL) in FIG. 4 represents a “neutral” threshold voltage value of memory cells of memory device 200. Value Vt_(NEUTRAL) may represent a neutral threshold voltage value of a memory cell when no charge (e.g., no extra electrons) or substantially no charge is present on the floating gate of the memory cell. The value of Vt_(NEUTRAL) may depend on the physical structure of the memory cell such as transistor channel length, width, and material doping concentration (e.g., doping concentration of a semiconductor material where the memory cells may be formed). In an example, the value of the neutral threshold voltage value (such as Vt_(NEUTRAL) of FIG. 4) of memory cells (e.g., memory cells 210, 211, 212, and 213) may be about zero volts to about one volt. In the example of FIG. 4, value Vt_(NEUTRAL) may be about 0.9 volt. Other values for Vt_(NEUTRAL) may be selected, including negative values.

As shown in FIG. 4, the threshold voltage values (Vt0 through Vt15) may change and move toward value Vt_(NEUTRAL) such that the threshold voltage values greater than value Vt_(NEUTRAL) (e.g., Vt15 and/or Vt14) may decrease in value, and the threshold voltage values less than value Vt_(NEUTRAL) (e.g., Vt1 and/or Vt2,) may increase in value. For example, as shown in FIG. 4, threshold voltage value Vt1 may increase in value (move up toward value Vt_(NEUTRAL) along the threshold voltage axis) while threshold voltage value Vt15 may decrease in value (move down toward value Vt_(NEUTRAL) along the threshold voltage axis). In FIG. 4, although each of threshold voltage values Vt0 through Vt15 may change in value, the value of each of threshold voltage values Vt0 through Vt15 before and after the change may still correspond to the same state. For example, as shown in FIG. 4, although threshold voltage value Vt1 may increase to threshold voltage value Vt′1, the values of Vt1 and Vt′1 may still correspond to the same state (e.g., state 1). In another example, as shown in FIG. 4, although threshold voltage value Vt15 may decrease to threshold voltage value Vt′15, the values of Vt15 and Vt′1 may still correspond to the same (e.g., state 15).

Since threshold voltage values Vt0 through Vt15 may change, the reliability of the information read from the selected memory cells may be maintained if new values (selected in ways described below) are used instead of the old values of V1 ₀, V1 ₁, and V1 ₂ through V1 ₁₅ because one or more of the old values may be inside, too close to, or too far from one or more ranges of the changed threshold voltage values (Vt′0 through Vt′15), thereby reading information from the selected memory cell using the old values (V1 ₀, V1 ₁, and V1 ₂ through V1 ₁₅) may give false or inaccurate results. Values V1′₀, V1′₁, and V1′₂ through V1′₁₅ in FIG. 4 may correspond to the new values of V1 ₀, V1 ₁, and V1 ₂ through V1 ₁₅. Each of values V1′₀, V1′₁, and V1′₂ through V1′₁₅ may correspond to one of values V1 ₀, V1 ₁, and V1 ₂ through V1 ₁₅ but may have a different value, and may change in the same direction as that of the corresponding threshold voltage values Vt0 through Vt15. For example, V1′₁ may correspond to V1 ₁ but have a value increased in the same direction as that of threshold voltage value Vt1, and V1′₁₅ may correspond to V1 ₁₅ but may have a value decreased in the same direction as that of threshold voltage value Vt15 decreasing to Vt′15. Memory device 200 (FIG. 2) may use V1′₀, V1′₁, and V1′₂ through V1′₁₅ during a read operation to read selected memory cells such as memory cells 211. Memory device 200 (FIG. 2) may operate to select the values of V1 (select values V1′₀, V1′₁, and V1′₂ through V1′₁₅) using a method similar to or identical to those described below with reference to FIG. 5.

FIG. 5 is a flow diagram showing methods 500 of selecting values for a voltage V1 to be applied to lines associated with selected memory cells of a memory device during a read operation according to an embodiment of the invention. The memory device used in methods 500 may be associated with memory device 200 of FIG. 2. The selected memory cells in methods 500 may be associated with memory cells 211 of FIG. 2. The unselected memory cells in methods 500 may be associated with memory cells 210, 212, and 213 of FIG. 2. Methods 500 may include at least three different ways to select values for voltage V1 (i.e., three different ways to select values V1′₀, V1′₁, and V1′₂ through V1′₁₅ of FIG. 4) with each of the three different ways being based on changes in the threshold voltage values of the memory cells.

Activity 510 of methods 500 may include performing at least one read operation to read selected memory cells of the memory device. Activity 510 may include starting to perform the read operation when the memory device receives a read command from an external device such as a processor. Activity 510 may include generating one or more internal read commands to perform the read operations for the purposes of selecting (e.g., calibrating) the values for voltage V1 as explained below. The internal read command(s) in activity 510 may be different from the (external) read command sent to the memory device by an external device. Activity 510, in some cases, may not operate to transfer the information read from the selected memory cells to terminals of the memory device (e.g., terminals similar to or identical to terminals 110 of FIG. 1) for further processing. Instead, methods 500 may use the information read by activity 510 for purposes of selecting values (performed by activity 520) for voltage V1. After engaging in activity 520, methods 500 may include performing a subsequent read operation (e.g., in activity 530) using the selected values for V1, and then transfer the information read in the subsequent read operation to other components (e.g., to the external device) for further processing. Methods 500 may include selecting the values for voltage V1 based on changes in the threshold voltage value with a highest value (e.g., Vt15) and the threshold voltage value with a lowest positive value (e.g., Vt1).

During a read operation, activity 510 may operate to apply voltage V1 to a line associated with the selected memory cells (e.g., a line similar to or identical to line 261 of FIG. 2). Activity 510 may then operate to apply a second voltage (e.g., similar to voltage V2) to other lines associated with the unselected memory cells (e.g., lines similar to or identical to lines 260, 262, and 263 of FIG. 2). Activity 510 may include performing more than one read operations to read the same selected memory cells but may use different set of values for voltage V1 (different sets of V1 ₀, V1 ₁, and V1 ₂ through V1 ₁₅) in different read operations within activity 510. The values of voltage V1 used in activity 510 may initially include the values V1 ₀, V1 ₁, and V1 ₂ through V1 ₁₅ (which are known values based on design and structures of the memory cells, as mentioned above with reference to FIG. 3). Activity 510 may include selectively increasing or decreasing one or more of values V1 ₀, V1 ₁, and V1 ₂ through V1 ₁₅ during the process of selecting the values for voltage V1. For example, activity 510 may use voltage V1 with value V1 ₁ of about 0.3 volt and value V1 ₁₅ of about 4.5 volts in a first read operation (and other appropriate values for V1 ₂ through V1 ₁₄). In a second read operation, activity 510 may operate to increase value V1 by an incremental value (e.g., 50 millivolts or some other incremental value) and to decrease V1 ₁₅ by a decremented value (e.g., 50 millivolts or other decremented value). Activity 510 may operate to increase and decrease the values of V1 ₁ and V1 ₁₅, respectively, because it may anticipate that the threshold voltage values (e.g., (Vt1 and Vt15) corresponding V1 ₁ and V1 ₁₅ may decrease or increase (e.g., may move toward the value Vt_(NEUTRAL)) as mentioned above in the description with respect to FIG. 4. Activity 510 may use the same known values for V1 ₀, V1 ₁, and V1 ₂, through V1 ₁₄. Activity 510 may also operate to appropriately increase or decrease the known values for V1 ₀, and V1 ₂ through V1 ₁₄, depending on each of these values relative to value Vt_(NEUTRAL).

Activity 510 may include tracking (e.g., storing) of values V1 ₁ and V1 ₁₅ (new values) from the read operations. For example, if activity 510 performs several read operations (in response to internal read commands), activity 510 may have several tracked values of V1 ₁ and several tracked values of V1 ₁₅. The tracked values of V1 ₁ and V1 ₁₅ refer to the values of V1 ₁ and V1 ₁₅ at which activity 510 successfully reads information from the selected memory cells. Activity 510 may select one of the tracked values of V1 ₁ and one of the tracked values of V1 ₁₅ for calculation (performed by activity 520 below) to select values (new values) for voltage V1 (e.g., V1′₀, V1′₁, and V1′₂ through V1′₁₅ of FIG. 4). Methods 500 may use the selected values of voltage V1 for one or more subsequent read operations (read operations performed after activity 510). In activity 510, if there are, for example, three tracked values of V1 ₁ with values 0.3 v, 0.35 v, and 0.4 v (“v” means volt) that activity 510 used to successfully read the information from the selected memory cells, then activity 510 may select the middle of V1 ₁ (or 0.35 v) to be used in the calculation to select the values for V1. In another example, if there are three tracked values of V1 ₁₅ with values 4.5 v, 4.45 v, and 4.4 v, then activity 510 may select the middle V1 ₁₅ or 4.45 v to be used in the calculation to select values for V1.

The reason for selecting the middle values is explained as follows. As shown in FIG. 4, value V1′₁ is between threshold voltage values Vt′1 and Vt′2. Since V1′₁ may be one of the three tracked values of V1 ₁, selecting the middle tracked values of V1 ₁ may reduce the chance of value V1′₁ (middle tracked value) being too close to either one of Vt′1 and Vt′2, thereby reading the information corresponding to threshold voltage values Vt′1 may reduce the chance for errors. Similarly, as shown in FIG. 4, value V′₁₅ is between threshold voltage values Vt′14 and Vt′15. Since V1′₁₅ may be one of the three tracked values of V1 ₁₅, selecting the middle tracked values of values of V1 ₁₅ may reduce the chance of value V1′₁₅ (middle tracked value) being too close to either one of Vt′14 and Vt′15, thereby reading the information corresponding to threshold voltage values Vt′15 may reduce the chance for errors. The number of tracked values (three) used in activity 510 is an example. Activity 510 may operate using only one tracked value. In such a case, the activity may operate to select that the tracked value to be used in the calculation to select values for V1.

As mentioned above, methods 500 may include three different ways to select values for voltage V1 (e.g., select values V1′₀, V1′₁, and V1′₂ through V1′₁₅).

Activity 520 of methods 500 may include selecting values (new values) for voltage V1 using calculations based on three expressions (1), (2), and (3) below.

Expression (1):

V1′_(n)=V1 _(n)−[[(V1 _(Z)−V1′_(Z))/Z]*n], where “Z” is one less than the number of threshold voltage values (or states), where “n” is an integer less than or equal to Z, and V1′_(n) corresponds to a value of voltage V1 that may be used to read the information corresponding to a threshold voltage value (or state) among “Z+1” threshold voltage values (or Z+1 states), e.g. threshold voltage values Vt′0 through Vt′15 when Z=15 for a 4-bit cell. Values V1 ₁ and V1 _(Z) are known values. Value V1′_(Z) may be obtained by activity 510 above. Based on expression (1), each of values of V1′₀, V1′₁, and V1′₂ through V1′₁₅ of voltage V1 may be calculated. For example, to calculate value V1′₂ (used to read the information corresponding to Vt2 or state 2), then n=2; to calculate V1′₁₄ (used to read the information corresponding to Vt2 or state 14) then n=14, and so on.

As shown in expression (1), to calculate the values V1′₀, V1′₁, and V1′₂ through V1′₁₅ of voltage V1 to read the information corresponding to Vt′0 through Vt′15, activity 520 may use the threshold voltage value with a highest value among the threshold voltage values (e.g., in FIG. 4, Vt′15 has a highest value among Vt′0 through Vt′15).

Expression (2):

V1′_(n)=V1 _(n)−[((V1 _(Z)−V1′_(Z))−(V1 ₁−V1′₁))/Z]*n, where “Z” is one less than the number of threshold voltage values (or states), where “n” is an integer less than or equal to Z, and V1′_(n) corresponds to a value of voltage V1 that may be used to read the information corresponding to a threshold voltage value among “Z+1” threshold voltage values. V1 ₁ and V1 ₁₅ are known values. V1′₁, and V1′₁₅ may be obtained by activity 510 above. Based on expression (2), each of values of V1′₀, V1′₁, and V1′₂ through V1′₁₅ of voltage V1 may be calculated. For example, to calculate value V1′₂, then n=2; to calculate V1′₁₄ then n=14, and so on.

As shown in expression (2), to calculate the values V1′₀, and V1′₁₅ of voltage V1 to read the information corresponding to Vt′0 through Vt′15, activity 520 may use the threshold voltage values with a highest value and a lowest positive value among the threshold voltage values (e.g., in FIG. 4, Vt′15 has a highest value among Vt′0 through Vt′15, and Vt′1 has a lowest positive value among Vt′0 through Vt′15)

Expression (3):

V1′_(n)=V1 _(n)−[((V1 _(Z)−V1′_(Z))/m)*(n−(15−m))], where “Z” is one less than the number of threshold voltage values (or states), where “n” is an integer less than or equal to Z, and V1′_(n) corresponds to a value of voltage V1 that may be used to read the information corresponding to a threshold voltage value among “Z+1” threshold voltage values. “m” is in an integer corresponding to the number of states between value Vt_(NEUTRAL) and the value of voltage V1 to read the information corresponding to the threshold voltage value having the highest value (e.g., value V1 ₁₅ in FIG. 3). V1 ₁ and V1 ₁₅ are known values. V1′₁ and V1′₁₅ may be obtained by activity 510 above. Based on expression (3), each of values V1′₀, V1′₁, and V1′₂ through V1′₁₅ of voltage V1 may be calculated. For example, if Vt_(NEUTRAL) (as shown in FIG. 3) is 0.9 volt, and V1 ₁ through V1 ₁₅ are linearly set on the vertical axis of FIG. 3 such that V1 ₁, V1 ₂, V1 ₃ (not shown in FIG. 3), V1 ₄ (not shown in FIG. 3), and V1 ₁₅ have known values of 0.3 v, 0.6 v, 0.9 v, 1.2 v, and 4.5 v, then the number of states (m) between value Vt_(NEUTRAL) and threshold voltage value V1 ₁₅ is m=12 (i.e., m includes state 4, state 5, and state 6 through state 15). In this example (Vt_(NEUTRAL) is 0.9 volt), to calculate value V1′₁₀, then in expression (3), n=2 and m=12. Thus, V1′₁₀=V1 ₁₀−[((V1 _(Z)−V1′_(Z))/12)*(10−(15−12)). By substituting appropriate values into expression (3), the value of V1′₁₄ may be calculated. Other values of V1′₁, and V1′₁₅ may be calculated in a similar manner.

In summary, activity 510 of methods 500 may perform at least one read operation to select values such as V1′₁, and V1′₁₅. And activity 520 may perform calculations based on expressions (1), (2), and (3) using V1′₁ and V1′₁₅ to select values for voltage V1 including V1′₀, V1′₁, and V1′₂ through V1′₁₅.

Activity 530 of methods 500 may include reading at least a portion of the memory cells of the memory device using the selected values for V1. For example, activity 530 may use the selected values to read selected memory cells (e.g., memory cells 211), and then transfer the information read from the memory cells to terminals of the memory device (e.g., terminals similar to or identical to terminals 110 of FIG. 1) for further processing. In another example, activity 530 may use the selected values to read other selected memory cells (e.g., memory cells 212) in response to another read command (different from the read command received by activity 510). Then, activity 530 may transfer the information read from the other selected memory cells (e.g., from memory cells 212) to terminals of the memory device (e.g., terminals similar to or identical to terminals 110 of FIG. 1) for further processing.

Methods 500 may include performing at least one of activities 510, 520, and 530 to select the values for voltage V1 (value V1′₀, V1′₁, V1′₂, and V1′₃ through V1′₁₅) every time the memory device receives a read command from an external device (e.g., a processor or a memory controller).

Methods 500 may also include performing at least one of activities 510, 520, and 530 in a time-based fashion (e.g., on a periodic basis, and not each and every instance the memory device receives a read command from an external device) to select the values for voltage V1. Methods 500 may store the selected values (store V1′₀, V1′₁, and V1′₂ through V1′₁₅), and then use the same stored values for different read operations in response to different read commands received by the memory device at different times. In this time-based operation, methods 500 may perform activity 510 after a selected time interval (e.g., X days, where X is a real number) to select new values for voltage V1 (new V1′₀, V1′₁, and V1′₂ through V1′₁₅) and then replace the stored values with the new values. The memory device may include a storage unit (similar to or identical to storage unit 120 of FIG. 1) to store the selected values for voltage V1 and the value for X. The value of X may determine when methods 500 may start to perform at least one of activities 510, 520, and 530 to select the values for voltage V1. The memory device may include a real-time clock to start methods 500 based on the value of X. For example, if X is 30 days, then every 30 days, methods 500 may perform at least one of activities 510, 520, and 530 to select the values for voltage V1. Thus, as described herein, X may be considered as an indication that may be stored such that methods 500 may perform at least one of activities 510, 520, and 530 to select the values for voltage V1 when X (the indication) reaches a selected time value (e.g., measured in X days or a fraction of a day, or X hours, etc.).

Methods 500 may operate to read only one group of selected memory cells (e.g., memory cells 211 in FIG. 2) to select the values for voltage V1 and then use the same selected values for other memory cells (e.g., memory cells 210, 212, and 213) when the other memory cells are selected to be read (e.g., in a subsequent read operation at another time).

Methods 500 may also operate to select the values of voltage V1 separately for each group of memory cells. For example, methods 500 may include performing at least one of activities 510, 520, and 530 four times to select four sets of values for voltage V1, where each set is selected from reading a corresponding selected group of memory cells in different read operation (e.g., read operation performed by activity 510). For example, methods 500 may select a first set of values of voltage V1 (a set of V1′₀, V1′₁, and V1′₂ through V1′₁₅) from reading for the group of memory cells 210, a second set of values of voltage V1 from reading for the group of memory cells 211, a third set of values of voltage V1 from reading for the group of memory cells 212, and a fourth set of values of voltage V1 from reading for the group of memory cells 213. In a subsequent read operation (e.g., read operation performed by activity 530), methods 500 may use the corresponding set of V1′₀, V1′₁, and V1′₂ through V1′₁₅ (e.g., first set) to read the corresponding group of memory cells (e.g., the group of memory cells 210).

The description above uses an example where each of the memory cells includes a 4-bit cell. Thus, methods 500 uses expressions (1), (2), and (3) above with values for a 4-bit per cell memory device. For a memory device with a different number of bits per cell, methods 500 may also use the expressions (1), (2), and (3) above, but with different values. For example, for a 3-bit cell memory device where each memory cell has a threshold voltage value corresponding to one of eight states (one of state 0 through state 7), methods 500 may use expressions (4), (5), and (6) based on expressions (1), (2), and (3) respectively, as follows. For eight states (i.e., substituting Z=7 in expressions (1), (2), and (3) above). V1′n=V1_(n)−[[(V1₇ −V1′₇)/7]*n]  (expression (4)) V1′_(n) =V1_(n)−[((V1₇ −V1′₇)−(V1₁ −V1′₁))/7]*n  (expression (5)) V1′_(n) =V1_(n)−[((V1₇ −V1′₇)/m)*(n−(7−m))],  (expression (6))

In the above description with reference to FIG. 5, methods 500 may select values for a voltage V1 that a memory device, such as memory device 200 of FIG. 2, may apply to a line associated with selected memory cells of a memory device during a read operation. For unselected memory cells, a memory device, such as memory device 200 of FIG. 2, may apply a voltage (e.g., voltage V2 of FIG. 2) with a value selected by a method described below with reference to FIG. 6.

FIG. 6 is a flow diagram showing methods 600 of selecting a value for a voltage V2 to be applied to lines associated with unselected memory cells of a memory device during a read operation according to an embodiment of the invention. The memory device used in methods 600 may be associated with memory device 200 of FIG. 2. The selected memory cells in methods 600 may be associated with memory cells 211 of FIG. 2. The unselected memory cells in methods 600 may be associated with memory cells 210, 212, and 213 of FIG. 2. Methods 600 may operate to select the value for V2 based on a result of at least one operation to check for errors in information read from the selected memory cells.

Activity 610 of methods 600 may include performing at least one read operation to read selected memory cells of the memory device (e.g., memory cells 211 of FIG. 2). Activity 610 may start performing the read operation when the memory device receives a read command from an external device such as a processor. Activity 610 may include generating one or more internal read commands to perform the read operations for the purposes of selecting (e.g., calibrating) the values for voltage V1 as explained below. The internal read command(s) may be different from the (external) read command sent to the memory device by an external device. In some cases, activity 610 may not operate to transfer the information read from the selected memory cells to terminals of the memory device (e.g., terminals similar to or identical to terminals 110 of FIG. 1) for further processing. Instead, methods 600 may use the information for purposes of selecting (e.g., calibrating) values for voltage V1. After activity 610, methods 600 may include performing a subsequent read operation (e.g., in activity 660) using the selected values for V1, and then transfer the information read in the subsequent read operation to other components (e.g., to the external device) for further processing.

During the read operation, activity 610 may include applying a voltage V1 to a line associated with the selected memory cells (e.g., lines similar to or identical to lines 261 of FIG. 1). The values of V1 may include V1 ₀, V1 ₁, V1 ₂ through V1 ₁₅ or V1′₀, V1′₁, AND V1′₂ through V1′₁₅ described above with reference to FIG. 4 and FIG. 5. Activity 610 in FIG. 6 may include applying a voltage V2 to lines associated with the unselected memory cells (e.g., lines similar to or identical to lines 260, 262, and 263 of FIG. 2).

Activity 620 may include checking for errors in information read from the selected memory cells. An error correction unit, such as error correction unit 118 of FIG. 1, may perform an error checking operation to check for errors and give a result. The information read from the selected memory cells may include a number of bits of data. Checking for errors in activity 620 may include identifying a failure bit quantity, which is a total number of bits (among the bits of data read from the selected memory cells) having errors. The value of the failure bit quantity may be zero, one, two, three, or some other value. Methods 600 may use the failure bit quantity as a result that other activities of methods 600, such as activity 630 below, may use.

Activity 630 may include determining whether the result (i.e., the failure bit quantity) satisfies a condition. The memory device used in methods 600 may set the condition in a storage unit such as storage unit 120 of FIG. 1. For example, the memory device may set the condition such that the result (obtained by activity 620) may satisfy the condition if at least one of the following is true: the failure bit quantity is equal to zero, the failure bit quantity is greater than zero and less than a particular value (e.g., greater than zero and less than eight), or the failure bit quantity is a lowest value among at least two failure bit quantities (e.g., failure bit quantities obtained from at least two read operations). Activity 630 may compare the result of checking for errors (e.g., value of the failure bit quantity) with the condition (e.g., a value stored in the storage unit). Depending on the outcome of the determination by activity 630, methods 600 may continue with either activity 640 or 650. For example, if the result satisfies the condition (indicated by “YES” in FIG. 6), methods 600 may continue with activity 650, and if the result does not satisfy the condition (indicated by “NO” in FIG. 6), methods 600 may continue with activity 640.

Activity 640 may includes changing the value of voltage V2 applied to the lines associated with the unselected memory cells. Activity 640 may change the value of voltage V2 by increasing the value of voltage V2. For example, if activity 610 (performed before activity 640) applied a value of 5.0 volts for voltage V2, then activity 640 here may increase the value of V2 to 5.2 volts. This example uses an increment of 0.2 volt. The incremental value, however, may vary (e.g., the incremental value is different from 0.2 volt, such as 0.1 volt or 0.3 volt or some other value). The incremental value may also be fixed or variable. For example, activity 640 may apply an incremental value of 0.2 volt to voltage V2 in a first read operation, and then apply a varying value of voltage V2, e.g., 0.3 volt (or some other value different from 0.2 volt) in a second read operation.

For each read operation, activity 640 may track the value of V2 and the value of the failure bit quantity, e.g., by storing these tracked values in registers or entering these values as entries in a table in the storage unit of the memory device. Thus, if activity 640 performs four read operations, then activity 640 may track (e.g., store) up to four values of V2 that are used in the four operations. For example, activity 640 may operate to record four tracked values such as 5.0 v, 5.2 v, 5.4 v, and 5.6 v after four read operations of the same selected memory cells.

After changing the value of voltage V2 and tracking the value in activity 640, methods 600 may repeat activities 610, 620, and 630 (and activity if 640 when the result does not satisfy the condition) until the result satisfies the condition or until a limited number of repeats is reached, then methods 600 may continue with activity 650.

Activity 650 may include selecting a value for voltage V2. As described above, activity 640 may track the values of V2 that are used in the read operations performed by activity 610. Activity 650 here may select from among the tracked values one that corresponds to the read operation with the failure bit quantity having the lowest value. Activity 650 may store the selected value for voltage V2 in a storage unit of the memory device. Methods 600 may use the selected value for voltage V2 for subsequent read operation (e.g., read operations performed by activity 660 below).

Activity 660 of methods 600 may include reading at least a portion of the memory cells of the memory device using the selected value for voltage V2. For example, activity 660 may use the selected value during reading of selected memory cells (e.g., memory cells 211), and then transfer the information read from the memory cells to terminals (e.g., terminals similar to or identical to terminals 110 of FIG. 1) for further processing. In another example, activity 660 may use the selected value during reading other selected memory cells (e.g., memory cells 212) in response to another read command (different from the read command received by activity 610). Then, activity 660 may transfer the information read from the other selected memory cells (e.g., from memory cells 212) to terminals (e.g., terminals similar to or identical to terminals 110 of FIG. 1) for further processing.

Methods 600 may perform at least one of activities 610, 620, 630, 640, and 650 to select the value for voltage V2 every time the memory device receives a read command from an external device (e.g., a processor or a memory controller).

Methods 600 may also perform at least one of activities 610, 620, 630, 640, and 650 in a time-based fashion (e.g., on a periodic basis, and not each and every instance the memory device receives a read command from an external device) to select the value for voltage V2. Methods 600 may store the selected value, and then use the same stored value for different read operations in response to different read commands received by the memory device at different times. In this time-based operation, methods 600 may perform activity 610 after each time interval (e.g., X days, where X is a real number) to select new value for voltage V2 and then replace the stored value with the new value. The memory device may include a storage unit (similar to or identical to storage unit 120 of FIG. 1) to store the selected value for voltage V2 and the value for X. The value of X may determine when methods 600 may start to perform at least one of activities 610, 620, 630, 640, and 650 to select the value for voltage V2. The memory device may include a real-time clock to start methods 600 based on the value of X. For example, if X is 30 days, then every 30 days, methods 600 may perform at least one of activities 610, 620, 630, 640, and 650 to select the value for voltage V2. Thus, as described herein, X may be considered as an indication to be stored, so that methods 600 may perform at least one of activities 610, 620, 630, 640, and 650 to check for the errors to select the value for voltage V2 when X (the indication) reaches a selected time value (e.g., measured in days or a fraction of a day, or X hours, etc.).

Methods 600 may operate to read only one group of selected memory cells (e.g., memory cells 211 in FIG. 2) to select the value for voltage V2 and then use the same selected value for other memory cells (e.g., memory cells 210, 212, and 213) when the other memory cells are selected to be read (e.g., in a subsequent read operation at another time).

Methods 600 may also operate to select the value of voltage V2 separately for each group of memory cells. For example, methods 600 may perform at least one of activities 610, 620, 630, 640, and 650 four times to select four values for voltage V2, where each value is selected from reading a corresponding selected group of memory cells in different read operation (e.g., read operation performed by activity 610). For example, methods 600 may operate to select a first value of voltage V2 from reading the group of memory cells 211, 212, and 213, a second value of voltage V2 from reading the group of memory cells 210, 212, and 213, a third value of voltage V2 from reading the group of memory cells 210, 211, and 213, and a fourth value of voltage V2 from reading the group of memory cells 210, 211, and 212. In a subsequent read operation (e.g., read operation performed by activity 660), methods 600 may use the corresponding selected value of V2 (first value) to read the corresponding group of memory cells (e.g., the group of memory cells 211, 212, and 213). In summary, the description above with reference to FIG. 6 shows a method of selecting a value for voltage V2. A memory device, such as memory device 100 or 200, may apply the selected value to lines associated with unselected memory cells during a read operation.

FIG. 7 shows a system 700 according to an embodiment of the invention. System 700 may include a processor 710, an image sensor device 720, a memory device 725, a memory controller 730, a graphics controller 740, an additional circuit 745, an input and output (I/O) controller 750, a display 752, a keyboard 754, a pointing device 756, a peripheral device 758, a transceiver 759, a bus 760 to transfer information among the components of system 700, and an antenna 770 to wirelessly transmit and receive information to and from system 700. Transceiver 759 may operate to transfer information from one or more of the components of system 700 (e.g., at least one of processor 710 and memory device 725) to antenna 770. Transceiver 759 may also operate to transfer information received at antenna 770 to at least one of the processor 710 and the memory device 725. The information received at antenna 770 may be transmitted to system 700 by a source external to system 700.

Processor 710 may include a general-purpose processor or an application specific integrated circuit (ASIC). Processor 710 may include a single core processor or a multiple-core processor. Processor 710 may execute one or more programming commands to process information. The information may include digital output information provided by other components of system 700, such as by image sensor device 720 or memory device 725.

Image sensor device 720 may include a complementary metal-oxide-semiconductor (CMOS) image sensor having a CMOS pixel array or charge-coupled device (CCD) image sensor having a CCD pixel array.

Memory device 725 may include a volatile memory device, a non-volatile memory device, or a combination of both. For example, memory device 725 may comprise a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or a combination of these memory devices. Memory device 725 may include one or more of the various embodiments described herein, such as memory devices 100 and 200.

Display 752 may include an analog display or a digital display. Display 752 may receive information from other components. For example, display 752 may receive information that is processed by one or more of image sensor device 720, memory device 725, graphics controller 740, and processor 710 to display information such as text or images.

Additional circuit 745 may include circuit components used in a vehicle. Additional circuit 745 may receive information from other components to activate one or more subsystem of the vehicle. For example, additional circuit 745 may receive information that is processed by one or more of image sensor device 720, memory device 725, and processor 710, to activate one or more of an air bag system of a vehicle, a vehicle security alarm, and an obstacle alert system.

The illustrations of apparatus (e.g., memory devices 100 and 200) and systems (e.g., system 700) are intended to provide a general understanding of the structure of various embodiments and are not intended to provide a complete description of all the elements and features of apparatus and systems that might make use of the structures described herein.

Any of the components described above can be implemented in a number of ways, including simulation via software. Thus, apparatus (e.g., a portion of memory device 100 or the entire memory device 100, and portion of memory device 200 or the entire memory device 200) and systems (e.g., a portion of system 700 or the entire system 700) described above may all be characterized as “modules” (or “module”) herein. Such modules may include hardware circuitry, single and/or multi-processor circuits, memory circuits, software program modules and objects and/or firmware, and combinations thereof, as desired by the architect of the apparatus (e.g., memory devices 100 and 200) and systems (e.g., system 700), and as appropriate for particular implementations of various embodiments. For example, such modules may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and distribution simulation package, a capacitance-inductance simulation package, a power/heat dissipation simulation package, a signal transmission-reception simulation package, and/or a combination of software and hardware used to operate or simulate the operation of various potential embodiments.

The novel apparatus and systems of various embodiments may include or be included in electronic circuitry used in high-speed computers, communication and signal processing circuitry, single or multi-processor modules, single or multiple embedded processors, multi-core processors, data switches, and application-specific modules including multilayer, multi-chip modules. Such apparatus and systems may further be included as sub-components within a variety of electronic systems, such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), set top boxes, and others

The embodiments described above with reference to FIG. 1 through FIG. 7 may include first memory cells and a first line used to access the first memory cells, second memory cells and at least one second line used to access the second memory cells. The first and second memory cells have a number of threshold voltage values corresponding to a number of states. The states represent values of information stored in the memory cells. During a read operation to read the first memory cells, a first voltage may be applied to the first line and a second voltage may be applied to the second line. At least one of the first and second voltages may include a value based on a change of at least one of the threshold voltage values from a first value to a second value. The first and second values may correspond to a unique state selected from the available states. Other embodiments including additional apparatus, systems, and methods are disclosed.

The above description and the drawings illustrate some embodiments of the invention to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may incorporate structural, logical, electrical, process, and other changes. In the drawings, like features or like numerals describe substantially similar features throughout the several views. Examples merely typify possible variations. Portions and features of some embodiments may be included in, or substituted for, those of others. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. Therefore, the scope of various embodiments of the invention is checked by the appended claims, along with the full range of equivalents to which such claims are entitled.

The Abstract is provided to comply with 37 C.F.R. §1.72(b) requiring an abstract that will allow the reader to quickly ascertain the nature and gist of the technical disclosure. The Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 

1. A method comprising: applying a first voltage to a first line used to access first memory cells of a memory device during a read operation to read the first memory cells; and applying a second voltage to a second line used to access second memory cells of the memory device during the read operation, the first and second memory cells having a number of threshold voltage values corresponding to a number of states, the number of states being greater than two, wherein the first voltage includes a value based on a change of at least one of the number of threshold voltage values including a first threshold voltage value changing from a first value to a second value, wherein the first and second values correspond to only one state of the number of states.
 2. The method of claim 1 comprising: reading at least one of the first memory cells and the second memory cells during at least one additional read operation, wherein the additional read operation is performed before the read operation to read the first memory cells; and selecting the value of the first voltage based on at least one value of the first voltage used during the reading of at least one of the first memory cells and the second memory cells.
 3. The method of claim 2, wherein reading at least one of the first memory cells and the second memory cells includes applying an initial value of the first voltage to one of the first and second lines during the additional read operation, and wherein the initial value of the first voltage is different from the value of the first voltage used during the read operation to read the first memory cells.
 4. The method of claim 2, wherein the read operation is performed in response to receiving a read command, and wherein the additional read operation is performed each time the read command is received.
 5. The method of claim 1, wherein the first threshold voltage value has a highest value among the number of threshold voltage values.
 6. The method of claim 1, wherein the change of at least one of the number of threshold voltage values further includes a second threshold voltage value of the number of threshold voltage values changing from a third value to a fourth value, and wherein the third and fourth values correspond to only one state of the number of states.
 7. The method of claim 6, wherein the first threshold voltage value has a highest value among the number of threshold voltage values, and wherein the second threshold voltage value has a lowest positive value among the number of threshold voltage values.
 8. A method comprising: applying a first voltage to a first line used to access first memory cells of a memory device during a read operation to read the first memory cells; and applying a second voltage to a second line used to access second memory cells of the memory device during the read operation, wherein the second voltage includes a value based on errors in information read from at least one of the first memory cells and the second memory cells.
 9. The method of claim 8, wherein each of the first and second memory cells has a threshold voltage value corresponding to one state of a number of states, the number of states being greater than two.
 10. The method of claim 8, wherein the errors include a failure bit quantity obtained from reading the first memory cells during at least one additional read operation performed before the read operation.
 11. The method of claim 10, wherein the read operation is performed in response to receiving a read command, and wherein the additional read operation is performed each time the read command is received.
 12. The method of claim 8, wherein the errors include a failure bit quantity, wherein the failure bit quantity has a lowest value among values of at least two failure bit quantities, and wherein the at least two failure bit quantities are obtained from reading the first memory cells during at least two additional read operations performed before the read operation.
 13. The method of claim 12 comprising: applying the second voltage with a first value to the second line when reading the first memory cells during a first additional read operation of the at least two additional read operations; and applying the second voltage with a second value to the second line when reading the first memory cells during a second additional read operation of the at least two additional read operations, wherein the first value is different from the second value.
 14. An apparatus comprising: first memory cells and a first line configured to access the first memory cells; second memory cells and at least one second line configured to access the second memory cells, the first and second memory cells configured to have a number of threshold voltage values corresponding to a number of states, the number of states being greater than two; and a module configured to apply a first voltage to the first line and a second voltage to the second line to read the first memory cells during a read operation, wherein the first voltage includes a value based on a change of at least one of the number of threshold voltage values including a first threshold voltage value of the threshold voltage values changing from a first value to a second value, wherein the first and second values correspond to only one state of the number of states.
 15. The apparatus of claim 14, wherein the module is configured to select the value of the first voltage based on a reading of at least one of the first memory cells and the second memory cells during an additional read operation, wherein the additional read operation is performed before the read operation.
 16. The apparatus of claim 14, wherein the module is configured to track values of the first voltage used during a reading of the first memory cells before the read operation.
 17. The apparatus of claim 15, wherein the module is configured to store an indication to perform the additional read operation when the indication reaches a selected time value.
 18. An apparatus comprising: first memory cells and a first line configured to access the first memory cells; second memory cells and at least one second line configured to access the second memory cells; and a module configured to apply a first voltage to the first line and a second voltage to the second line to read the first memory cells during a read operation, wherein the second voltage includes a value based on errors in information read from at least one of the first memory cells and the second memory cells.
 19. The apparatus of claim 18, wherein the first memory cells and the second memory cells are configured to have a number of threshold voltage values corresponding to a number of states, the number of states being greater than two.
 20. The apparatus of claim 18, wherein the module is configured to track values of the second voltage used during a reading of the first memory cells before the read operation.
 21. The apparatus of claim 18, wherein the module is configured to store an indication to perform an additional read operation to check for the errors when the indication reaches a time value.
 22. The apparatus of claim 18 comprising an additional module configured to check for the errors used in association with selecting the value for the second voltage.
 23. A system comprising: a flash memory device including: first memory cells and a first line configured to access the first memory cells; and second memory cells and at least one second line configured to access the second memory cells, the first memory cells and the second memory cells configured to have a number of threshold voltage values corresponding to a number of states, the number of states being greater than two; and a module configured to apply a first voltage to the first line and a second voltage to the second line to read the first memory cells during a first read operation, wherein the first voltage includes a value based on a change of at least one of the threshold voltage values among the number of threshold voltage values changing from a first value to a second value, wherein the first and second values correspond to only one state of the number of states, and wherein the second voltage includes a value based on a failure bit quantity in information read from at least one of the first memory cells and the second memory cells in a second read operation performed before the first read operation; and a processor configured to process the information stored in the flash memory device.
 24. The system of claim 23 comprising: a transceiver coupled to the flash memory device.
 25. The system of claim 23 comprising: a pixel array coupled to the flash memory device. 